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Avtomatika i Telemekhanika, 2017, Issue 1, Pages 121–136 (Mi at14661)  
This article is cited in 5 scientific papers (total in 5 papers)

Logic Control

Data processing in the firmware systems for logic control based on search networks

V. Sklyarov, I. Skliarova

Universidade Aveiro, Instituto di Electrónica et Informática, Aveiro, Portugal
Full-text PDF (4199 kB) Citations (5)
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Abstract: It was proposed to use the hardware accelerators for analysis and data processing in the systems of logic control on a chip including the interacting processor system, memory, and configurable logic components. The data processing expected execution of operations over the sets of elements each of which can be activated by software and realized in the hardware in parallel networks admitting, if necessary, pipeline processing. New methods of design and use of the sorting and search networks were proposed, and the results of their theoretical and experimental comparison with the existing networks were presented.
Keywords: data processing, search networks, hardware accelerators, firmware systems.
Presented by the member of Editorial Board: V. M. Vishnevsky

Received: 12.10.2015
English version:
Automation and Remote Control, 2017, Volume 78, Issue 1, Pages 100–112
DOI: https://doi.org/10.1134/S0005117917010088
Bibliographic databases:
Document Type: Article
Language: Russian
Citation: V. Sklyarov, I. Skliarova, “Data processing in the firmware systems for logic control based on search networks”, Avtomat. i Telemekh., 2017, no. 1, 121–136; Autom. Remote Control, 78:1 (2017), 100–112
Citation in format AMSBIB
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  • https://www.mathnet.ru/eng/at/y2017/i1/p121
    • This publication is cited in the following 5 articles:
    1. Valery Sklyarov, Iouliia Skliarova, Irbulat Utepbergenov, 2021 IEEE 15th International Conference on Application of Information and Communication Technologies (AICT), 2021, 1  crossref
    2. I. Skliarova, V. Sklyarov, “Architectures of fpga-based hardware accelerators and design techniques”: Skliarova, I Sklyarov, V, Fpga-Based Hardware Accelerators, Lecture Notes in Electrical Engineering, 566, Springer, 2019, 39–67  crossref  isi  scopus
    3. Sklyarov V., Skliarova I., “Network-Based Priority Buffer”, 2017 5Th International Conference on Electrical Engineering - Boumerdes (Icee-B), Mediterranean Conference on Control and Automation, IEEE, 2017, 939–944  isi
    4. Sklyarov V., Skliarova I., “Network-Based Priority Buffer”, 2017 5Th International Conference on Electrical Engineering - Boumerdes (Icee-B), IEEE, 2017  isi
    5. Valery Sklyarov, Iouliia Skliarova, 2017 5th International Conference on Electrical Engineering - Boumerdes (ICEE-B), 2017, 1  crossref
    Citing articles in Google Scholar: Russian citations, English citations
    Related articles in Google Scholar: Russian articles, English articles
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    Abstract page:387
    Full-text PDF :102
    References:62
    First page:25
     
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